Accurate Leakage-Conscious Architecture-Level Power Estimation Models for On-Chip SRAM Memory Arrays

Perhaps reinforced by the notion of a Moore’s Law, technology scaling has provided the IC industry with an integration capacity of billions of transistors. As transistors keep shrinking in size, leakage power dissipation dramatically increases and gradually becomes a first-class design constraint in more and more designs. To provide higher performance at lower power and energy for micro-architectures, on-chip memories are growing in size and thus become a major contributor to the total leakage power dissipation in next-generation processors. In these circumstances, accurate leakage power estimation obviously is needed to allow designers to strike a balance between dynamic power and leakage power, and between total power and delay in onchip SRAM memory. Since all leakage mechanisms are closely related to the physical behavior of MOSFET transistors, circuit-level simulators are needed to maintain a high accuracy in estimating leakage power dissipation. However, this high accuracy comes at an extremely high cost in the form of computational complexity, since circuit simulators are built on very complex, technology-dependent and detailed analytical/empirical power models, e.g. BSIM3 or BSIM4 [1]. Obviously, circuit simulation is seldom a viable solution when simulating digital circuit blocks, let alone big onchip memories. At the other end of the accuracy spectrum, we have simplified analytical leakage power models, e.g. CACTI4.0 [3] power models. But such models are neither suitable to the conflicting requirements enforced on leakage power estimation: high accuracy, flexibility and simplicity. Solving these conflicting requirements is the topic that our research work targets. We propose a modular, hybrid power modeling methodology capable of capturing accurately both dynamic and leakage power mechanisms for on-chip SRAM arrays. The methodology successfully combines the most valuable advantage of circuit-level power estimation – high accuracy – with the flexibility of higher-level power estimation, while allowing for short component characterization and estimation time. Rather than using only one technique to estimate power dissipation, the proposed methodology seeks to find the best match between a particular estimation technique and a specific SRAM array component. For example, a probabilistic approach has been used to estimate both dynamic and static power of address decoders, an analytical approach has been used to estimate dynamic power of bitlines and 6T-SRAM cells, sense amplifiers, write circuits, and wordline drivers, while a circuit-simulationbased modeling backend has been used to estimate all leakage power mechanisms. Furthermore, the proposed modeling methodology is modular and, thus, it can be applied to model power dissipation for other types of regular structures, e.g. content-addressable-memory (CAM). The initial idea of the modeling methodology has been discussed in Paper 1, where the White-box Table-based Total Power Consumption estimation approach (WTTPC) is introduced. Further development on the idea of the WTTPC approach leads to the formation of the modeling methodology for un-partitioned data SRAM arrays; this is fully described in Paper 2. Finally, the modeling methodology for physically partitioned data SRAM arrays is developed and described in Paper 3. The proposed methodology offers high-level parameterizable, but still accurate power dissipation estimation models that consist of analytical equations for dynamic power and pre-characterized leakage power values stored in tables. Through verification for a number of on-chip SRAM array configurations implemented in 0.13-μm and 65-nm CMOS processes, the proposed power models show a high accuracy in estimating both dynamic and static power for all the SRAM array components. In addition, a modeling methodology to capture the dependence of leakage power on supply-voltage scaling has also been presented. This methodology provides an essential extension to the proposed power models. The proposed power modeling methodology and power models, as far as we know, are the first ones that can offer high-level, parameterizable, relatively simple and highaccuracy power estimation models for on-chip SRAM arrays accounting for both dynamic and static power consumption. Our on-going research work is targeting methods to provide architectural power models for TAG arrays for complete on-chip cache organizations as well as architectural models that can account also for process variations. 1. Advisor Information Advisor: Per Larsson-Edefors, Professor Dept. of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Göteborg, Sweden. Email: [email protected] Co-Advisor: Lars Bengtsson, Associate Professor Dept. of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Göteborg, Sweden. Email: [email protected] 2. Personal Information Name: Minh Q. Do, PhD student Phone: +46 31 772 5216; Fax: +46 31 772 3663 URL: www.ce.chalmers.se/∼minh Estimated graduation date: June 2007 This research work has not been presented at any ASP-DAC PhD Forum or DATE PhD Forum. 3. List of Related Published Papers The result of my research work is based on the following published papers: Paper 1: M. Q. Do, P. Larsson-Edefors and L. Bengtsson, “Table-based Total Power Consumption Estimation of Memory Arrays for Architects,” in Proceedings of the 14 International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Isle of Santorini, Greece, Sept. 15–17, 2004, pp. 869–878. Paper 2: M. Q. Do, M. Draždžiulis, P. Larsson-Edefors and L. Bengtsson, “Parameterizable Architecture-level SRAM Power Model Using Circuit-simulation Backend for Leakage Calibration,” in Proceedings of International Symposium on Quality Eletronic Design (ISQED), San Jose, CA, USA, March 27-29, 2006, pp. 557–563. Paper 3: M. Q. Do, M. Draždžiulis, P. Larsson-Edefors and L. Bengtsson, “Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays,” in Proceedings of International Symposium on Quality Eletronic Design (ISQED), San Jose, CA, USA, March 26-28, 2007. (nominated as a candidate for the best-paper-award) 4. Description of the Supporting Paper The supporting paper (i.e. Paper 3) presents the modeling methodology and power dissipation estimation models for physically partitioned data SRAM arrays. These arrays can be partitioned both horizontally, using a divided word-line (DWL) technique [4], and vertically, using a hierarchical divided bit-line (DBL) technique [2]. Since the partitioning enforces substantial modifications to the power models for some array components, this paper shows the manner in which our modeling methodology is applied to obtain power models for those components. The obtained models offer accurate estimation of both dynamic and leakage power, including the power dissipation due to emerging leakage mechanisms such as gate oxide tunneling. It also accounts for partitioned arrays that deploy data-retaining sleep techniques for leakage reduction. The validation has been done against circuit simulations for a complete partitioned 8-kBytes 6T-SRAM array implemented in a commercial 0.13-μm process, achieving very high degree of accuracy (97%). In addition, this paper also presents a modeling methodology to capture the dependence of leakage power on supply-voltage scaling.